The present invention relates to a semiconductor memory device, and more particularly, to a MOS type programmable read-only memory (ROM).
Generally, each memory cell of the MOS type programmable ROM is a double-gate, transistor cell which has a floating gate 14 electrically isolated from other elements of the cell, as is illustrated in FIG. 1. The transistor cell comprises p-type semiconductor substrate 11, n-type impurity regions 12 and 13 formed in the surface of substrate 11, floating gate 14 formed on an oxide film (not shown) formed on the surface of substrate 11, and control gate 15 formed on an oxide film (not shown) formed on floating gate 14. N-type impurity regions 12 and 13 function as a source region and a drain region, respectively, and set apart for a predetermined distance. Floating gate 14 is located above that portion of substrate 11 separating regions 12 and 13. Control gate 15 is positioned above floating gate 14.
In order to write data into the memory cell, a high voltage is applied beween control gate 15 and drain region 13, thereby imparting great energy to the electrons moving between drain region 13 and source region 12. The energized electrons move into floating gate 14. In other words, the electrons are injected into floating gate 14.
The speed of injecting the electrons into floating gate 14 has been raised by reducing the size of the memory cell, or by reducing the thickness of the oxide films formed on and under gate 14. The time required for writing data into the memory cell has therefore been shortened. However, the memory cell of the structure shown in FIG. 1 is disadvantageous. The electrons can move from floating gate 14 through the oxide film formed on or under this gate, when data is written into any other memory cell connected to the same word gate line or the same bit line. This is because, when the data is written in the other memory cell, a high voltage is inevitably applied to the control gate or drain region of the first memory cell. This undesired phenomenon will be explained in greater detail, with reference to FIG. 2.
FIG. 2 shows a semiconductor memory device comprising word lines WL1 and WL2, bit lines BL1, and BL2, and memory cells M11, M12, M21 and M22 arranged in rows and columns. The control gates of memory cells M11 and M12, forming the first row, are coupled to word line WL1. The control gates of memory cells M21 and M22, following the second row, are connected to word line WL2. The drains of memory cells M11 and M21, forming the first column, are coupled to bit line BL1. The drains of memory cells M12 and M22, forming the second column, are coupled to bit line BL2. The memory device further comprises selection transistors Q1, Q2 . . . Qn. These transsitors Q1, Q2 . . . Qn are connected at one end to bit lines BL1, BL2 . . . BLn, respectively, and at the other end to writing-voltage terminal Vpp by load transistor QD. Transistor QD is controlled by control signal D.
Now, assume that data is first written into memory cell M11 and then into memory cell 21. First, a high voltage is applied between word line WL1 and bit line BL1. All other word lines and all other bit lines are set at 0V. As a result, the data is written into memory cell M11. Then, the high voltage is applied between word line WL1 and bit line BL2, thereby writing data into memory cell M21. This high voltage is applied to the controlg gate of memory cell M11 although the data need not be written in memory cell M11. Consequently, the electrons may drain from the floating gate of memory cell M11 through the oxide film formed on the floating gate, under the influence of the electric field generated between the control gate and floating gate of memory cell M11 through the oxide film formed on the floating gate, under the influence of the electric field generated between the control gate and floating gate of memory cell M11, unless the oxide film between the floating and control gates of memory cell M11 has a sufficient insulating strength.
Assume that data is first written into memory cell M11 and then into memory cell 12. In this case, a high voltage is applied between word line WL2 and bit line BL1 after data has been written into memory cell M11. The high voltage is also applied to the drain of memory cell M11. Consequently, the electrons may move from the floating gate of cell M11 to the drain of cell M11 unless the oxide film formed between the drain and floating gates has a sufficient insulating strength.
In either case, the data cannot be successfully written in memory cell 11. The longer the time for writing data in each memory cell, the more frequently the data cannot be written. Therefore, MOS type programmable ROMs are tested before they are delivered to the customers, by applying data-writing voltage to them for the time specified in the test manual, although the time actually required for writing data into the memory cells can be much shorter. This test procedure must be performed in order not to deliver MOS type programmable ROMs which have failed to store the data, due to the undesired phenomenon that electrons drain out of the floating gates of some memory cells.
It has been proposed that a so-called "gate-stress circuit" or a so-called "drain-stress circuit" be used in order to check the phenomenon effectively. The gate-stress circuit responds to a special control signal supplied from an external device, and applies a high voltage to all word gate lines of the MOS type programmable ROM and also resets all bit lines of the ROM at 0V. After electrons have been injected into the floating gates of all memory cells of the ROM within a short data-writing time, the gate-stress circuit is operated to set the floating gates of the memory cells at 0V and to set the control gates of the memory cells at a high voltage level. Hence, it can be quickly determined whether or not electrons have drained out of the floating gates of the memory cells due to the insufficient insulating strength of the oxide film interposed between the floating gates, on the one hand, and the control gates, on the other.
The drain-stress circuit applies a high voltage to all bit lines of the MOS type programmable ROM, in response to a control signal supplied from an external device. When the circuit applies the high voltage to the drain lines, all word lines are set at 0V. As a result, it can be determined whether or not electrons have drained from the floating gates of the memory cells due to the insufficient insulating strength of the oxide film provided between the floating gates, on the one hand, and the control gates, on the other.
As has been stated, when the drain-stress circuit applied the high voltage to the drain lines, the control gates of all memory cells are set at 0V. Therefore, none of the cells are turned on, and the voltage applied to the drain lines is inevitably higher than the voltage which will be applied to the drain lines to write data in the cells. In the case of the memory device shown in FIG. 2, a high voltage is applied to the drain of memory cell M11 after data has been written in memory cell M11, in order to write data in memory cell M12. At this time, memory cell M12 is turned on since a high voltage is applied to its control gate. The drain voltage is applied to its control gate. The drain voltage of memory cell M12 is divided by the ratio of the resistance of load transistor QD to the resistance of memory cell M12. Here arises a problem. Due to the use of the drain-stress circuit, none of the memory cells are turned on, and all cells are tested with a drain voltage higher than the data-writing drain voltage. It is therefore possible that the memory device is regarded as storing erroneous data, even if it stores the correct data when operated under the normal condition.